Integrated circuits use output drivers to drive off-chip loads. This can involve driving capacitances of up to 100 pf (pico-farads). To quickly charge up such a load requires sourcing and sinking a large current into the load. This situation is expressed by the relationship dv/dt=I/C. However, because of the inductance of the bond wires and lead frame, a changing current in the output driver will produce a voltage change on the power supply (V.sub.CC) or ground (GND) pins. This phenomena is known as V.sub.CC bounce and ground bounce, respectively. The induced voltage (V) on the V.sub.CC or GND pin is proportional to the rate of change of the current, and is given by V=-L di/dt, where L is the inductance of the bond wires and/or lead frame.
Ground bounce is a problem for at least two reasons. Because it changes the voltage seen at the output of the driver with respect to ground, and because multiple drivers typically share a common ground connection, the ground bounce from a driver switching can change the outputs of the other drivers sharing the same ground connection. This may make another integrated circuit on the same printed circuit board see an incorrect voltage level. An even bigger problem (because the voltage spike is larger on the integrated circuit side of a parasitic inductor compared to the ground side) is that multiple output drivers often have an input buffer connected to a common pad. This is done to implement bi-directional input/output operations. As a result, a voltage spike on the ground connection may make the input buffer assert an incorrect level.
Multiple output drivers switching in the same direction each contribute to the changing current. Therefore, the overall current change with time (di/dt) gets multiplied for every output driver on the same V.sub.CC or V.sub.SS connection. This suggests minimizing the induced voltage by reducing the number of output drivers sharing a common connection. However, a conflicting trade-off is that it is desirable to minimize the pin count of an integrated circuit; thus, it is desirable to share as many input/output pads as possible with a common ground or power supply pin.
Another consideration is that, for an integrated circuit to be able to drive a capacitive load fast enough at slow PVT (process-voltage-temperature), the output driver must be sufficiently large. However, for such a large output driver used at fast PVT, the di/dt will be greater, causing more ground and power supply bounce.
One method of addressing the ground and power supply bounce problem is to utilize open loop control of the output stage rate of change of Vgs (d(Vgs)/dt). This method is based on providing slew rate limiting of the voltage applied to the gates of the output stage. By limiting the rate at which Vgs changes, the rate of change of the current in the output stage is limited (since Id=K(Vgs-Vt).sup.2), This technique creates bias voltages vbias.sub.-- p and vbias.sub.-- such that the slew rate of the current starved inverters in the output driver is constant over PVT, and is typically implemented using a bandgap reference.
However, a disadvantage of this technique is that the "on" resistance of certain of the inverters still has some influence on the slew rate, and because voltages vbias.sub.-- n and vbias.sub.-- p are only subjected to open loop control, the optimal slew rate may not be realized over varying PVT. Another disadvantage is that the bias circuit requires extensive redesign when the input/output cell is ported to a new process.
Another attempted solution to the ground and power supply bounce problems is to artificially increase the resistance in series with the parasitic inductance arising from the bond wires or lead frame. This method is implemented by adding a resistor in series with the ground and V.sub.CC lines internal to the integrated circuit, with the resistance placed between the output driver transistors and the ground/V.sub.CC pads. This damps the noise (voltage) spikes caused by a rapidly changing current. A disadvantage of this approach is that it reduces the VOL/VOH margins by creating an IR voltage drop. Another disadvantage is that the damping depends on the value of R, which is only loosely controlled over various processes.
Yet another approach to the ground and power supply bounce problem is to use multiple, staggered output drivers. This method breaks the output stage into multiple stages that turn on one after another. This distributes the changing current over a greater time period, reducing the magnitude of the (di/dt) term and hence the induced voltage which causes the ground (or power supply) bounce. A disadvantage of this approach is that the staggering amount is PVT dependent. Another disadvantage is that the staggering is performed in an open loop manner.
A possible improvement to this approach is discussed in the article entitled "A Low Power-Noise Output Driver with an Adaptive Characteristic Applicable to a Wide Range of Loading Conditions", IEEE Journal of Solid State Circuits, Vol. 32, #6 June 1997. The article describes the use of feedback control to choose how many output stages actually get turned on. However, the granularity is only one or two stages.
What is desired is a circuit that reduces the ground and/or power supply bounce which arises from a changing current in an output driver, and which overcomes the disadvantages of the known methods.